人体模型(HBM)论文(有全文）

 1 A comparison of quasi-static characteristics and failure signatures of GMR heads subjected to CDM and HBM ESD events
2 Influence of the charging effect on HBM ESD device testing
3 A study of ESD sensitivity in AMR and GMR recording heads
4 ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness
5 Comparison and correlation of ESD HBM (human body model) obtained between TLPG, wafer-level, and package-level tests
6 A method for determining a transmission line pulse shape that produces equivalent results to human body model testing methods
7 ESD testing of GMR heads as a function of temperature
8 A study of head stack assembly sensitivity to ESD
9 Analysis of HBM and MM ESD failures in nMOS devices
10 Electrostatic discharge testing of tunneling magnetoresistive (TMR) devices
11 ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness
12 TLP calibration, correlation, standards, and new techniques [ESD test]
13 ESD-level circuit simulation-impact of gate RC-delay on HBM and CDM behavior
14 Investigation of GMR sensor microstructural changes induced by HBM ESD using advanced microscopy approach
15 Pitfalls when correlating TLP, HBM and MM testing
17 Thermal breakdown of VLSI by ESD pulses
18 A sub-1-dB NF±2.3-kV ESD-protected 900-MHz CMOS LNA
19 Comparison between the effects of positive noncatastrophic HBM ESD stress in n-channel and p-channel power MOSFETs
20 ESD robustness of smart-power protection structures evaluated by means of HBM and TLP tests
21 In-situ spin stand ESD testing of giant magnetoresistive (GMR) recording heads
22 A study of wafer level ESD testing
25 A new algorithm for circuit-level electrothermal simulation under EOSESD stress
26 Electrostatic discharge (ESD) sensitivity of thin films hybrid passive components
27 TLP calibration, correlation, standards, and new techniques
28 A study of ESD protection devices for input pins. Discharge characteristics of diode, lateral bipolar transistor, and thyristor under MM and HBM te
29 Grounded-gate nMOS transistor behavior under CDM ESD stress conditions
30 Electrostatic discharge (ESD) sensitivity of thin-film hybrid passive components
31 Cancellation technique to provide ESD protection for multi-GHz RF inputs
32 Extended harmonic balance method
33 ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins
34 Failure analysis of ESD damage in a high-voltage driver IC and the effective ESD protection solution [CMOS]
35 A hybrid buffer cache management scheme for VOD server
37 Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes
38 Considerations for an HBM ESD standard for measuring and testing of magneto resistive heads
39 An analytical model of positive HBM ESD current distribution and the modified multi-finger protection structure
40 Bipolar model extension for MOS transistors considering gate coupling effects in the HBM ESD domain
41 A simulation study of HBM failure in an internal clock buffer and the design issues for efficient power pin protection strategy
42 High voltage resistant ESD protection circuitry for 0.5 μm CMOS OTP EPROM programming pin
43 A comparison of electrostatic discharge models and failure signatures for CMOS integrated circuit devices
44 ESD failure mechanisms of inductive and magnetoresistive recording heads
45 Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high low-voltage-tolerant IO interface
46 On a dual-polarity on-chip electrostatic discharge protection structure
47 Hierarchical basis multilevel preconditioners for 3D magnetostatic problems
48 Area-efficient layout design for CMOS output transistors
49 ESD protection for output pad with well-coupled field-oxide device in 0.5-μm CMOS technology
52 A low-voltage triggering SCR for on-chip ESD protection at output and input pads
55 ESD challenges in magnetic recording past, present and future
56 Improving the scalability of an application-level group communication protocol
57 Bonding-pad-oriented on-chip ESD protection structures for ICs
58 An integrated 5.2GHz CMOS T R switch with LC-tuned substrate bias
59 Ku-band low noise amplifier with using short-stub ESD protection
60 The influence of process and design of subcollectors on the ESD robustness of ESD structures and silicon germanium heterojunction bipolar transisto
61 A novel motion estimation algorithm using phase plane correlation for frame rate conversion
62 Complementary substrate-triggered SCR devices for on-chip ESD protection circuits
63 Drain profile engineering of RESURF LDMOS devices for ESD ruggedness
65 On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process
66 High voltage tolerant ESD design for analog applications in deep submicron CMOS technologies
67 Improvement of degradation detection in ESD test for semiconductor products
68 A novel CDM-like discharge effect during human body model (HBM) ESD stress
69 ESD protection of RF circuits in standard CMOS process
70 ESD protection design for mixed-voltage IO circuit with substrate-triggered technique in sub-quarter-micron CMOS process
71 Novel ESD protection structure with embedded SCR LDMOS for smart power technology
72 ESD protection strategy for sub-quarter-micron CMOS technology gate-driven design versus substrate-triggered design
73 ESD protection design in a 0.18-μm salicide CMOS technology by using substrate-triggered technique
74 Design on ESD protection circuit with very low and constant input capacitance
75 A novel SCR macromodel for ESD circuit simulation
76 Electrostatic discharge characterization of epitaxial-base silicon-germanium heterojunction bipolar transistors
77 On-chip ESD protection design by using polysilicon diodes in CMOS technology for smart card application
79 Baseline popping of spin-valve recording heads induced by ESD
80 ESD damage thresholds history and prognosis [magnetic heads]
81 ESD evaluation of tunneling magnetoresistive (TMR) devices
82 An anti-snapback circuit technique for inhibiting parasitic bipolar conduction during EOSESD events
83 A study of fully silicided 0.18 μm CMOS ESD protection devices
84 Analyzing the switching behavior of ESD-protection transistors by very fast transmission line pulsing
85 Conductive floor and footwear system as primary protection against human body model ESD event
86 Wide range control of the sustaining voltage of ESD protection elements realized in a smart power technology
87 Analysis and compact modeling of lateral DMOS power devices under ESD stress conditions
88 Experimental investigation on the HBM ESD characteristics of CMOS devices in a 0.35-μm silicided process
89 Characterization and optimization of a bipolar ESD-device by measurements and simulations
90 A substrate triggered lateral bipolar circuit for high voltage tolerant ESD protection applications
91 Cross-referenced ESD protection for power supplies [microprocessors]

 

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